This application relates generally to non-volatile semiconductor memories of the flash memory type, their formation, structure and use.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, USB drives, embedded memory, and Solid State Drives (SSDs) which use an array of flash EEPROM cells. An example of a flash memory system is shown in FIG. 1, in which a memory cell array 1 is formed on a memory chip 12, along with various peripheral circuits such as column control circuits 2, row control circuits 3, data input/output circuits 6, etc.
One popular flash EEPROM architecture utilizes a NAND array, wherein a large number of strings of memory cells are connected through one or more select transistors between individual bit lines and a reference potential. A portion of such an array is shown in plan view in FIG. 2A. Although four floating gate memory cells are shown in each string, the individual strings typically include 16, 32 or more memory cell charge storage elements, such as floating gates, in a column. Control gate (word) lines labeled WL0-WL3 and string selection lines, Drain Select Line, “DSL” and Source Select Line “SSL” extend across multiple strings over rows of floating gates. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard by placing a relatively high voltage on their respective word lines and by placing a relatively lower voltage on the one selected word line so that the current flowing through each string is primarily dependent only upon the level of charge stored in the addressed cell below the selected word line. That current typically is sensed for a large number of strings in parallel, thereby to read charge level states along a row of floating gates in parallel.
The top and bottom ends of the string connect to the bit line and a common source line respectively through select transistors (source select transistor and drain select transistor) in which the floating gate material (P1) is in direct contact with the control gate material (P2) through an opening formed in interpoly dielectric (IPD) material. The active gate thus formed is electrically driven from the periphery. Transistors in peripheral circuits are similarly formed by connecting floating gate material, P1, to overlying control gate material, P2, to form an active gate.
Select transistors and peripheral circuits are formed on the same chip as the memory cells but they have very different functions that require different device structures. Thus, a process that is adapted for forming a memory array may not be ideal for forming peripheral circuits and vice versa. In general, the cost of manufacturing a memory chip increases with the number of processing steps used, and the number of defective units may tend to increase also. So it is desirable to use the same process steps for both the memory array and peripheral circuits.
Thus, there is a need for a memory chip manufacturing process that forms the memory cells, select transistors, and peripheral circuits in an efficient manner and there is a need for structures that can be formed accordingly.